1. Field of the Invention
The invention lies in the field of integrated circuits. More specifically, the invention pertains to an integrated buffer circuit with an input inverter, a feedback inverter, and an output inverter. The integrated buffer circuit has the following characteristics:
the input inverter is a CMOS inverter and includes at least one transistor of one conductivity type and one other transistor of the other conductivity type, with the gates of the transistors connected to an input terminal of the circuit; PA0 the output inverter is connected in series in terms of signals to the input inverter via a circuit node and is connected by its output to an output terminal of the circuit; PA0 an input of the feedback inverter is connected to the output terminal and an output of the feedback inverter is connected to the circuit node; and PA0 the source terminal of the other transistor of the input inverter is connected to a first supply potential. PA0 a CMOS input inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first and second transistors each having a gate connected to an input terminal of the circuit; PA0 an output inverter connected in series between the input inverter and an output terminal of the circuit; PA0 a feedback inverter having an input connected to the output terminal and an output connected to a circuit node between the input inverter and the output inverter; PA0 a source of the second transistor being connected to a first supply potential; and PA0 a series circuit for limiting a rest current through the input inverter connected between a second supply potential and the source terminal of the first transistor of the input inverter, the series circuit including at least a transistor, connected as a diode, and an ohmic resistor.
Various families of circuits have become established in the course of the development of integrated circuitry. The various circuit families are distinguished from one another by their circuit concepts, integration density, and electrical data. There are differences particularly in the level of the operating voltages.
The first generation of integrated circuits, which has gained wide use, is that of bipolar TTL low-scale and medium-scale integrated circuits, particularly for digital applications. Even today, the first generation is still important and can be found along with CMOS circuits that were developed later. Both TTL logic and CMOS logic can also be found inside one circuit. The various operating voltages of these circuit families must be taken into account, and level conversion is necessary. So-called buffers are used to convert the TTL level to the internal CMOS level in the chip.
European patent disclosure EP 0 587 938 A1 discloses an integrated buffer circuit with two series-connected inverters. The first inverter is a CMOS inverter. The output signal of the second inverter is positively fed back via a further inverter to the input signal of the second inverter. A constant current source impresses a constant current into the channel-side path of the first inverter. With the aid of enable transistors, the first inverter and a constant current source can be turned off, thus increasing the efficiency of the input signal of the buffer circuit, at times when intensive disturbances can be expected. A disadvantage of the known buffer circuit is its high rest current, which primarily flows as transverse current through the first inverter, when a TTL signal at a high level is present at the input of the buffer circuit and therefore the transistors of the CMOS inverter are conducting.
When no switching signal is expected, the buffer circuit can be inactivated and the rest current lowered via the enable transistors. To control the enable transistors, a signal must be present. Applications exist in which such a signal cannot be made available. In dynamic memories, for instance, the RAS control signal, which controls loading the address into the address register and addressing the row to be addressed in the memory matrix, is weighted by an RAS buffer, or in other words, the state of the RAS control signal is evaluated continuously, which precludes inactivation of the buffer.